Intel is striving to regain the industrial discipline it lost amidst delays, CPU/GPU revisions, and products that haven’t always met expectations. Current Intel CEO, Lip-Bu Tan, has decided to convey this message directly to internal teams with a statement that leaves little room for interpretation: if a chip, whether CPU or GPU, goes beyond B0 revision, engineers will be dismissed.
The declaration was made at a J.P. Morgan conference, where Tan discussed the necessity of transforming Intel’s validation culture. The objective is to deliver cleaner designs to manufacturing, with fewer errors, fewer revisions, and less room for late problem-solving.
Tan Imposes Faster Pace and Fewer Errors at Intel: Layoffs for Engineers with B0 Chips
There’s no doubt that Intel needed a firmer hand, as the company has teetered on the brink of being acquired multiple times, plummeting from grace. AMD has significantly outperformed Intel in CPUs, and NVIDIA has dashed its few hopes in GPUs. Therefore, Tan was exceptionally clear and resolute at the conference, signaling a tough approach from the outset by implementing a new working method:
“One thing about timelines: I have a culture that I’ve just implemented. It needs to be from A0 to production.”
What does A0 refer to? For those unfamiliar, A0 is the first physical version of a chip after tape-out. Tape-out is the point at which the design is finalized and sent for manufacturing. If all goes well, this initial silicon boots up, functions, and allows progress without major changes. Achieving this on the first attempt with complex chips like modern CPUs is far from simple, making it crucial for avoiding delays.
When a chip doesn’t perform well enough at A0, new revisions are made, known as steppings. B0 would represent a second major revision. C0, D0, or higher imply more corrections, more time, more cost, and a greater risk of delays. While these aren’t necessarily negative, they become problematic when they occur on the first attempt, highlighting the importance of A0.
Cutting Timelines, Improving Design and Production Chain Efficiency, No Room for Error
The issues faced over a decade ago with lithographic nodes, specifically the delay in adopting EUV technology, are closely related to the work philosophy and opportunity cost, where the acceptable failure rate was too high. This is precisely what Tan aims to prevent within Intel.
“Intel didn’t have that culture, and I’m imposing it.”
This statement is particularly stark because it doesn’t target a specific chip but rather a way of working. Tan is indicating that Intel was not organized to take its designs to production from the first pass. This is especially critical for a company aiming to fiercely compete again in both CPUs and foundry services for third parties.
“So I say this: first pass, A0. B0, you keep your job. Anything beyond that, you’re fired.”
Tan also explained that initially, some within Intel thought he was exaggerating or joking, but the message was serious. The idea is to review the complete design, pending bugs, and utilized IP before tape-out, to avoid discovering critical issues only after the chip has already been manufactured.
“You review the entire design, all the bugs we try to fix, and all the IP we use; there can be no error.”
The underlying message is quite clear and equally direct to its engineers. Intel no longer wants to incur months of delays for every validation error. A0 must be the target, B0 the tolerable limit, and anything beyond that signifies that something went significantly wrong early in the process. If any engineer or group of engineers exceeds B0 on their chips, Intel will formalize dismissals, as Tan is providing advance warning. A tough approach is returning to Intel; the initial results will be seen in upcoming architectures, with their new CEO spearheading this new work culture.
