Huawei has unveiled a new strategy to continue advancing chip manufacturing despite U.S. technological blockades. The key lies in Huawei not promising to manufacture chips with a true 1.4nm node, but rather to design chips whose transistor density is equivalent to that of a 14 Å / 1.4 nm process by 2031. This is an important distinction: Huawei is attempting to compensate for its limitations in advanced lithography with improvements in architecture, interconnection, packaging, circuit design, and system-level optimization.
This proposal comes in a very clear context. China continues to face significant difficulties in accessing EUV lithography machinery and other critical advanced manufacturing technologies due to U.S. restrictions. Without this machinery, manufacturing chips at process nodes below 7nm is, for now, nearly impossible. Although it is indicated that the company is leveraging TSMC’s current machinery for 7nm DUV chips to add improvements that would allow them to manufacture 5nm chips, reports suggest the yield rate (percentage of functional chips per wafer) is very low.
Tau Scaling Law: Huawei’s Alternative to Moore’s Law for Advancing the Chip Industry Despite US Blockade
According to Huawei, the industry can no longer rely solely on reducing transistor size. Therefore, the next leap must come from reducing the time it takes for data and signals to move within chips, circuits, devices, and complete systems. In other words, it’s not just about “making it smaller,” but about making everything communicate faster and with less latency.
Huawei explains that the Tau Scaling Law is supported by many layers. This includes optimization of transistors and interconnections, reduction of resistive and capacitive loads, co-design between software, architecture, and silicon, and new interconnection protocols like UnifiedBus for SuperPoD-type systems. In practice, the idea is to cut internal bottlenecks to increase performance, efficiency, and effective density, even if manufacturing is not at the level of TSMC, Samsung, or Intel.
The most striking associated technology is LogicFolding, an architecture that Huawei will debut in upcoming Kirin chips planned for autumn 2026. According to the company, LogicFolding allows for shortening critical wiring within the chip, reducing signal propagation delay, and significantly improving both density and performance. Huawei also claims that over the past six years, it has designed and mass-produced 381 chips based on this philosophy for sectors such as smartphones and AI. With this technology, the company promises to improve density by 53% and increase clock speeds by 12.7%.
We Will Have to Wait to See if Huawei is Truly Capable of Offering Performance Equivalent to 1.4nm
Huawei is not claiming that China can manufacture true 1.4nm chips in the short term. The approach is that it aims to achieve equivalent density through design, architecture, and system optimization by 2031. The difference is key: it’s not about having 1.4nm lithography like TSMC, but about trying to compensate for the limitations imposed by U.S. sanctions with techniques such as better interconnections, lower internal latency, and more efficient designs.
The central figure in this strategy is He Tingbo, head of Huawei’s semiconductor business and one of HiSilicon’s key architects. Her role gained importance after the 2019 sanctions, when Huawei was forced to accelerate its technological independence. Now, with the so-called Tau Scaling Law, the company is attempting to transform that survival strategy into a technical roadmap to compete in the post-Moore’s Law era.
The goal is not limited to its HiSilicon Kirin mobile chips, of course. Huawei’s primary incentive is to strengthen its Ascend chip line as a Chinese alternative to NVIDIA in AI. This is especially relevant at a time when U.S. restrictions and pressure from Beijing are pushing China towards domestic solutions. The real takeaway is that Huawei is proposing an interesting path to reduce the technological gap without relying solely on smaller nodes. In other words, the current bottleneck is the inability to access ASML’s most advanced lithography machines, which prevents it from competing on equal terms with the rest of the industry. Tau Scaling Law aims to eliminate this bottleneck.
